1. Field of the Invention
The present invention relates to semiconductor devices and method of fabricating the same and, more particularly, to Complementary Metal Oxide semiconductor (CMOS) devices having elevated source/drain regions and methods of fabricating the same.
2. Description of the Related Art
Metal Oxide Semiconductor (MOS) transistors are widely employed as discrete devices of semiconductor devices. As semiconductor devices have become more highly integrated, MOS transistors have been scaled down. In particular, the channel length of MOS transistors have been reduced to implement a high performance semiconductor device. However, when the channel length of an MOS transistor is reduced, the MOS transistor typically suffers from a short channel effect. Accordingly, to improve the short channel effect, the junction depth of source/drain regions of the MOS transistors also needs to be reduced. That is, to fabricate high performance MOS transistors, there is a need for a method of forming shallow source/drain regions. Nevertheless, even shallow source/drain regions may lead to increase of on-resistance of the MOS transistors. The increase of the on-resistance may in turn lead to degradation of the current drivability of the MOS transistor.
Accordingly, an elevated source/drain structure has been designed to suppress the above-mentioned short channel effect and improve the current drivability. This elevated source/drain structure has been designed by a widely known technique called selective epitaxial growth.
The above selective epitaxial growth technique is disclosed in U.S. Pat. No. 6,429,084 B1 to Park et al., entitled “MOS Transistors with Raised Sources and Drains”. Park et al. purports to disclose forming a gate capping insulating layer on a gate electrode. The gate capping insulating layer prevents an epitaxial semiconductor layer on source/drain regions from being formed on the gate electrode during formation of the epitaxial semiconductor layer. However, in the event that a metal silicide layer is formed on the gate electrode in a subsequent process, an additional complicated process may be required to form its MOS transistor with raised source and drain regions.
In addition, a method of forming the elevated source/drain regions is disclosed in U.S. Patent Publication No. US 2002/0034864 A1 to Mizushima et al., entitled “Semiconductor Device and Method of Fabricating the Same”. Mizushima et al. purports to disclose using a blanket deposition technique to form an amorphous silicon layer on an entire surface of a semiconductor substrate having a polysilicon gate electrode and single crystalline source/drain regions. The amorphous silicon layer is crystallized using a solid phase epitaxial (SPE) technique. As a result, only the amorphous silicon layer on the single crystalline source/drain regions is crystallized to form elevated single crystalline source/drain regions. Moreover, the amorphous silicon layer on the polysilicon gate electrode may be converted into a polycrystalline silicon layer or kept the same in an amorphous state.
Further, according to conventional methods such as those described in Mizushima, the amorphous silicon layer (or the polycrystalline silicon layer) on the gate electrode is selectively removed using a hydrogen chloride (HCl) gas. The single crystalline silicon layer on the source/drain regions is then crystallized using a single step solid phase epitaxial process. Mizushima also describes that the single crystalline silicon layer is formed evenly on an isolation layer adjacent to the source/drain regions. However, a difficulty with the above process described in Mizushima, is that when the width of the isolation layer is reduced in order to fabricate a highly integrated semiconductor device, an electrical shortage may occur between the source/drain regions formed at both sides of the isolation layer.
Conventional elevated source/drain regions, such as those described above, may be employed in both N-Channel Metal Oxide Semiconductor (NMOS) transistors and Positive Channel Metal Oxide Semiconductor (PMOS) transistors. Moreover, MOS transistors having the elevated source/drain regions include insulating gate spacers provided on sidewalls of the gate electrode to form Lightly Doped Drain (LDD) type source/drain regions, with a salicide (self-aligned silicide) technique applied thereto. The gate spacers electrically insulate the gate electrode from the elevated source/drain regions.
However, in conventional semiconductor devices, when the width of the gate spacers increases, coupling capacitance between the gate electrode and the elevated source/drain regions decreases, and electrical resistance of the LDD type source/drain regions increases. As a result, the operating speed of the NMOS transistors is typically improved, whereas an operating speed of the PMOS transistors is typically degraded, because a mobility of electrons acting as carriers of the NMOS transistors is larger than a mobility of holes acting as carriers of the PMOS transistors. In other words, in conventional semiconductor devices, the operating speed of the NMOS transistors depends on parasitic capacitance between the gate electrode and the source/drain regions rather than the electrical resistance of the source/drain regions, and the operating speed of the PMOS transistors depends on electrical resistance of the source/drain regions rather than the parasitic capacitance between the gate electrode and the source/drain regions. Therefore, there is a need for optimizing the operating characteristics of both the NMOS transistors and the PMOS transistors that employ the elevated source/drain regions.